Document
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad Latch
The MC10168 is a Quad Latch with common clocking to all four latches. Separate output enabling gates are provided for each latch, allowing direct wiring to a bus. When the clock is high, outputs will follow the D inputs. Information is latched on the negative–going transition of the clock.
PD = 310 mW typ/pkg (No Load) tpd = G to Q = 2 ns typ
D to Q = 3 ns typ C to Q = 4 ns typ tr, tf = 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
D0 3
G0 5 G1 4
Q0 Q1
D1 7 CC 13 D2 9
G2 12 G3 10
Q2 Q3
D3 14
VCC1 = PIN 1 VCC2 = PIN 16
VEE = PIN 8
TRUTH TABLE
GCD HXX
Qn+1 L
LLX LHL
Qn L
LHH
H
2 Q0 6 Q1
11 Q2 15 Q3
MC10168
P SUFFIX PLASTIC PACKAGE
CASE 648–08
PIN ASSIGNMENT
VCC1 Q0 D0 G1 G0 Q1 D1
VEE
1 2 3 4 5 6 7 8
16 VCC2 15 Q3 14 D3 13 CC 12 G2 11 Q2 10 G3 9 D2
9/96
© Motorola, Inc. 1996
3–99
REV 6
MC10168
ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Pin Under Test
–30°C Min Max
Power Supply Drain Current Input Curre.