S29PL032J

S29PL-J 128-/64-/32-Mbit (8/4/2M × 16-Bit), 3 V, Flash with Enhanced VersatileIO™ S29PL-J, 128-/64-/32-Mbit (8/4/2M × 16-Bit), 3 V, Flash with Enhanced VersatileIO™ Distinctive Characteristics Architectural Advantages ■ 128-/64-/32-Mbit Page Mode devices ❐ Page size of 8 words: Fast page read access from random locations within the page ■ Single power supply operation ❐ Full Voltage range: 2.7 to 3.6 V read, erase, and program operations for battery-powered applications ■ Simultaneous Read/Write Operation ❐ Data can be continuously read from one bank while executing erase/program functions in another bank ❐ Zero latency switching from write to read operations ■ FlexBank Architecture (PL127J/PL064J/PL032J) ❐ 4 separate banks, with up to two simultaneous operations per device ❐ Bank A: PL127J -16 Mbit (4 Kw  8 and 32 Kw  31) PL064J - 8 Mbit (4 Kw  8 and 32 Kw  15) PL032J - 4 Mbit (4 Kw  8 and 32 Kw  7) ❐ Bank B: PL127J - 48 Mbit (32 Kw  96) PL064J - 24 Mbit (32 Kw  48) PL032J - 12 Mbit (32 Kw  24) ❐ Bank C: PL127J - 48 Mbit (32 Kw  96) PL064J - 24 Mbit (32 Kw  48) PL032J - 12 Mbit (32 Kw  24) ❐ Bank D: PL127J -16 Mbit (4 Kw  8 and 32 Kw  31) PL064J - 8 Mbit (4 Kw  8 and 32 Kw  15) PL032J - 4 Mbit (4 Kw  8 and 32 Kw  7) ■ Enhanced VersatileI/O (VIO) Control ❐ Output voltage generated and input voltages tolerated on all control inputs and I/Os is determined by the voltage on the VIO pin ❐ VIO options at 1.8 V and 3 V I/O for PL127J devices ❐ 3V VIO for PL064J ...