2.5V / 3.3V Dual Channel Programmable Clock/Data Delay
NB6L295M
2.5V / 3.3V Dual Channel
Programmable Clock/Data
Delay with Differential CML
Outputs
Multi−Level Inputs w/...
Description
NB6L295M
2.5V / 3.3V Dual Channel
Programmable Clock/Data
Delay with Differential CML
Outputs
Multi−Level Inputs w/ Internal Termination
The NB6L295M is a Dual Channel Programmable Delay Chip
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designed primarily for Clock or Data de−skewing and timing
adjustment. The NB6L295M is versatile in that two individual variable delay channels, PD0 and PD1, can be configured in one of
MARKING DIAGRAM*
two operating modes, a Dual Delay or an Extended Delay.
24
In the Dual Delay Mode, each channel has a programmable delay section which is designed using a matrix of gates and a chain of multiplexers. There is a fixed minimum delay of 3.2 ns per channel.
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QFN−24 MN SUFFIX CASE 485L
1 NB6L 295M ALYWG
The Extended Delay Mode amounts to the additive delay of PD0 plus PD1 and is accomplished with the Serial Data Interface MSEL bit set High. This will internally cascade the output of PD0 into the input of PD1. Therefore, the Extended Delay path starts at the I...
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