MC10E154

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 5ĆBit 2:1 MuxĆLatch The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW. 850ps Max. LEN to Output 825ps Max. D to Output Differential Outputs Asynchronous Master Reset Dual Latch-Enables Extended 100E VEE Range of – 4.2V to – 5.46V 75kΩ Input Pulldown Resistors MC10E154 MC100E154 5-BIT 2:1 MUX-LATCH Pinout: 28-Lead PLCC (Top View) D4b D4a D3b D3a VCCO Q4 Q4 25 24 23 22 21 20 19 SEL 26 18 Q3 LEN1 27 17 Q3 LEN2 28 16 VCC VEE 1 15 Q2 MR 2 14 Q2 D0a 3 13 Q1 D0b 4 12 Q1 5 6 7 8 9 10 11 D1a D1b D2a D2b VCCO Q0 Q0 * All VCC and VCCO pins are tied together on the di...