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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
6ĆBit D Register
The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 (or both) go HIGH. The asynchronous Master Reset (MR) makes all Q outputs go LOW.
• 1100MHz Min. Toggle Frequency • Differential Outputs • Asynchronous Master Reset • Dual Clocks • Extended 100E VEE Range of – 4.2V to – 5.46V • 75kΩ Input Pulldown Resistors
LOGIC DIAGRAM
D0 D
Q0
R Q0
MC10E151 MC100E151
6-BIT D REGISTER
D1 D
Q1
R Q1
FN SUFFIX PLASTIC PACKAGE
CASE 776-02
D2 D
Q2
R Q2
D3 D
Q3
R Q3
D4 D
Q4
R Q4
D5 D
Q5
R Q5
CLK1 CLK2
MR
PIN NAMES
Pin Function
D0 – D5 CLK1, CLK2
MR
Q0 – Q5 Q0 – Q5
Data Inputs Clock Inputs Master Reset True Outputs Inverted Outputs
12/93
© Motorola, Inc. 1996
2–1
Pinout: 28-Lead PLCC (Top View) MR CLK2 CLK1 NC VCCO Q5 Q5
25 24 23 22 21 20.