Document
M24C01/02-W M24C01/02-R M24C02-F
Datasheet
1-Kbit and 2-Kbit serial I²C bus EEPROMs
TSSOP8 (DW) 169 mil width
SO8N (MN) 150 mil width
UFDFPN8 (MC) DFN8 - 2 x 3 mm
UFDFPN5 (MH) DFN5 - 1.7 x 1.4 mm
Product status link M24C01-W M24C02-W M24C01-R M24C02-R M24C02-F
Product label
Features
I2C interface • Compatible with following I2C bus modes:
– 400 kHz (Fast mode) – 100 kHz (Standard mode)
Memory • 1-Kbit (128-byte) of EEPROM • 2-Kbit (256-byte) of EEPROM • Page size: 16-byte
Supply voltage • Wide voltage range: From 1.6 V to 5.5 V
– M24C01/02-W: 2.5 V to 5.5 V – M24C01/02-R: 1.8 V to 5.5 V – M24C02-F:
1.7 V to 5.5 V 1.6 V to 5.5 V (under temperature constraint)
Temperature • Operating temperature range: from -40 °C up to +85 °C
Fast write cycle time
• Byte and page write within 5 ms
Performance • Enhanced ESD/latch-up protection • More than 4 million write cycles • More than 200-year data retention
Advanced features • Random and sequential read modes • Hardware write protection of the whole memory array • Enhanced ESD/latch-Up protection
Packages Packages RoHS-compliant and Halogen-free • SO8N (ECOPACK2) • TSSOP8 (ECOPACK2) • UFDFPN8 (ECOPACK2) • UFDFPN5 (ECOPACK2)
DS9398 - Rev 8 - July 2023 For further information contact your local STMicroelectronics sales office.
www.st.com
M24C01/02-W M24C01/02-R M24C02-F
Description
1
Description
The M24C01(C02) is a 1(2)-Kbit I2C-compatible EEPROM (electrically erasable programmable memory) organized as 128 (256) × 8 bits.
The M24C01/02-W can be accessed with a supply voltage from 2.5 V to 5.5 V, the M24C01/02-R can be accessed with a supply voltage from 1.8 V to 5.5 V, and the M24C02-F can be accessed either with a supply voltage from 1.7 V to 5.5 V (over the full temperature range) or with an extended supply voltage from 1.6 V to 5.5 V under some restricted conditions. These devices operate with a maximum clock frequency of 400 kHz.
Figure 1. Logic diagram VCC
3 E0-E2
SCL WC
M24xxx
SDA
VSS
Table 1. Signal names
Signal name
E2, E1, E0(1)
Chip enable
SDA
Serial data
SCL
Serial clock
WC
Write control
VCC
Supply voltage
VSS
Ground
1. Signal not connected in the DFN5 package.
Function
Input I/O Input Input -
Figure 2. 8-pin package connections, top view
Direction
E0 1 E1 2 E2 3 VSS 4
8 VCC 7 WC 6 SCL 5 SDA
1. See Package information for package dimensions, and how to identify pin 1
DT01845fV1
DS9398 - Rev 8
page 2/41
M24C01/02-W M24C01/02-R M24C02-F
Description
Figure 3. UFDFPN5 (DFN5) package connections
VCC 1 VSS 2 SDA 3
ABCD XYZW
5 WC 2 VSS 4 SCL
5
1
2
2
4
3
Top view (marking side)
Bottom view (pads side)
1. Inputs E2, E1, E0 are not connected. Refer to Section 4.5 Device addressing for further explanations.
DS9398 - Rev 8
page 3/41
2
Signal description
M24C01/02-W M24C01/02-R M24C02-F
Signal description
2.1 2.2 2.3
2.4
2.5 2.6
2.6.1
Serial clock (SCL)
The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out).
Serial data (SDA)
SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wired-AND with other open drain or open collector signals on the bus. A pull-up resistor must be connected from serial data (SDA) to VCC (Figure 11 indicates how to calculate the value of the pull-up resistor).
Chip enable (E2, E1, E0)
(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to VCC or VSS, as shown in Table 2. When not connected (left floating), these inputs are read as low (0). For the UFDFPN5 package, the (E2,E1,E0) inputs are not connected.
Write control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when write control (WC) is driven high. Write operations are enabled when write control (WC) is either driven low or left floating. When write control (WC) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged.
VSS (ground)
VSS is the reference for all signals, including the VCC supply voltage.
Supply voltage (VCC)
Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8 DC and AC parameters). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tW).
DS9398 - Rev 8
page 4/41
.