Document
Semiconductor
CD74HC393, CD74HCT393
High Speed CMOS Logic Dual 4 -Stage Binary Counter
Description
The Harris CD74HC393 and CD74HCT393 are 4-stage ripple-carry binary counters. Al counter stages are masterslave flip-flops. The state of the stage advances one count on the negative transition of each clock pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered.
September 1997
Features
• Fully Static Operation • Buffered Inputs • Common Reset • Negative-Edge Clocking • Typical fMAX = 60 MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Ordering Information
PART NUMBER CD74HC393E CD74HCT393E CD74HC393M CD74HCT393M NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer or die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld PDIP 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC PKG. NO. E14.3 E14.3 M14.15 M14.15
Pinout
CD74HC393, CD74HCT393 (PDIP, SOIC) TOP VIEW
1CP 1 1MR 2 1Q0 3 1Q1 4 1Q2 5 1Q3 6 GND 7 14 VCC 13 2CP 12 2MR 11 2Q0 10 2Q1 9 2Q2 8 2Q3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© Harris Corporation 1997
File Number
1653.1
1
CD74HC393, CD74HCT393 Functional Diagram
3 1Q0 1 1CP 2 1MR BINARY COUNTER 4 1Q1 5 1Q2 6 1Q3 11 13 2CP 12 2MR BINARY COUNTER 10 9 8
2Q0 2Q1 2Q2 2Q3
GND = 7 VCC = 14
TRUTH TABLE OUTPUTS CP COUNT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CP COUNT ↑ ↓ X Q0 L H L H L H L H L H L H L H L H MR L L H Q1 L L H H L L H H L L H H L L H H Q2 L L L L H H H H L L L L H H H H OUTPUT No Change Count LLLL Q3 L L L L L L L L H H H H H H H H
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High Level, ↓ = Transition from High to Low.
2
CD74HC393, CD74HCT393 Logic Diagram
Φ
Q
Φ
Q
Φ
Q
Φ
Q
1(13) CP
Φ R
Q
Φ R
Q
Φ R
Q
Φ R
Q
2(12) MR
3(11) Q0 Q1
4(10) Q2
5(9) Q3
6(8)
3
CD74HC393, CD74HCT393
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode .