Document
A29L001 Series
128K X 8 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
Document Title 128K X 8 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
Revision History
Rev. No.
0.0 0.1
1.0
History
Initial issue Change device ID to EDh (Top boot) and 6Dh (Bottom boot) on Table 5. Final version release
Issue Date
August 28, 2014 November 12, 2014
Remark
Preliminary
December 7, 2015
Final
(December, 2015, Version 1.0)
AMIC Technology, Corp.
AMIC reserves the right to change products and specifications discussed herein without notice.
A29L001 Series
128K X 8 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
Features
Single power supply operation
- 2.7 to 3.6 volt for 0°C ~ +70°C - 3.0 to 3.6 volt for -40°C ~ +85°C (-U) Access times: - 70ns (max.) Current: - 20mA typical active read current - 30mA typical program/erase current
- 6μA typical CMOS standby Flexible sector architecture
- 8 Kbyte/ 4 KbyteX2/ 16 Kbyte/ 32 KbyteX3 sectors - Any combination of sectors can be erased - Supports full chip erase - Sector protection:
A hardware method of protecting sectors to prevent any inadvertent program or erase operations within that sector Unlock Bypass Program Command - Reduces overall programming time when issuing multiple program command sequence Top or bottom boot block configurations available Embedded Erase Algorithms - Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors - Embedded Program algorithm automatically writes and verifies bytes at specified addresses
Minimum 100,000 program/erase cycles per sector 20-year data retention at 125ºC
- Reliable operation for the life of the system Compatible with JEDEC-standards
- Pinout and software compatible with single-powersupply Flash memory standard
- Superior inadvertent write protection
Data Polling and toggle bits
- Provides a software method of detecting completion of program or erase operations
Erase Suspend/Erase Resume - Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation
Hardware reset pin (RESET )
- Hardware method to reset the device to reading array data
Industrial operating temperature range: -40°C to
+85°C for – U Package options
- 32-pin P-DIP, PLCC or TSOP - All Pb-free (Lead-free) products are RoHS2.0 compliant
General Description
The A29L001 is a 3.0 volt-only Flash memory organized as 131,072 bytes of 8 bits each. The A29L001 offers the RESET function. The 128 Kbytes of data are further divided into seven sectors for flexible sector erase capability. The 8 bits of data appear on I/O0 - I/O7 while the addresses are input on A0 to A16. The A29L001 is offered in 32-pin PLCC, PDIP and TSOP packages. This device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29L001 can also be programmed in standard EPROM programmers. The A29L001 has the first toggle bit, I/O6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O6 toggle bit, the A29L001 has a second toggle bit, I/O2, to indicate whether the addressed sector is being selected for erase. The A29L001 also offers the ability to program in the Erase Suspend mode. The standard A29L001 offers access time of 70ns allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable ( CE ), write enable ( WE ) and output enable ( OE ) controls.
The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The A29L001 is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin. Device erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed)
(December, 2015, Version 1.0)
1 AMIC Technology, Corp.
before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin.
The host syst.