A25LQ64

A25LQ64 Series 64M-BIT (x1 / x2 / x4) 3.3V CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY Document Title 64M-BIT (x1 / x2 / x4) 3 . 3 V CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY Revision History Rev. No. 0.0 0.1 0.2 0.3 0.4 0.5 1.0 1.1 1.2 1.3 1.4 History Initial issue Add 16-pin SOP (300mil) package type Add 8-pin SOP (209mil) package type Add FAST READ DUAL OUTPUT (3Bh) command Refine QE bit definition to control only hardware protect function Change Figure-36-1, 36-2 and refine erase cycling Final version release SFDP address 08h ID code 37 changed to 00 SFDP address 38h & 4Ah EB dummy code data bits 04~00 changed from 00110b to 00100b Add A25LQ64M-FE type in ordering information This type fixes QE bit “1” The hardware protect function is disabled in this type Add 8-pin DIP package type Modify the fast program time spec. Change Figure 7. unique ID to 64 bytes Issue Date June 2, 2012 June 28, 2012 July 10, 2012 November 1, 2012 November 19, 2012 January 14, 2013 March 5, 2013 May 9, 2013 July 01, 2013 January 9, 2014 July 3, 2014 Remark Preliminary Final (July, 2014, Version 1.4) AMIC Technology Corp. A25LQ64 Series 64M-BIT (x1 / x2 / x4) 3.3V CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY FEATURES GENERAL „ Serial Peripheral Interface compatible -- Mode 0 and Mode 3 „ 64Mb: 67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O mode) structure or 16,777,216 x 4 bits (four I/O mode) structure „ Equal Sectors with 4K byte each, or Equal Blocks with 32K byte eac...