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SK70706 Dataheets PDF



Part Number SK70706
Manufacturers Intel
Logo Intel
Description 784 Kbps HDSL Data Pump Chip Set
Datasheet SK70706 DatasheetSK70706 Datasheet (PDF)

SK70704/SK70706 784 Kbps HDSL Data Pump Chip Set Datasheet The HDSL Data Pump is a chip set consisting of the following two devices: s SK70704 Analog Core Chip (ACC) s SK70706 HDSL Digital Transceiver (HDX) The HDSL Data Pump is a 2-wire transceiver which provides echo-cancelling and 2B1Q line coding. It incorporates transmit pulse shaping, filtering, line drivers, receive equalization, timing and data recovery to provide 784 kbps, clear-channel, “data pipe” transmission. The Data Pump provides .

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SK70704/SK70706 784 Kbps HDSL Data Pump Chip Set Datasheet The HDSL Data Pump is a chip set consisting of the following two devices: s SK70704 Analog Core Chip (ACC) s SK70706 HDSL Digital Transceiver (HDX) The HDSL Data Pump is a 2-wire transceiver which provides echo-cancelling and 2B1Q line coding. It incorporates transmit pulse shaping, filtering, line drivers, receive equalization, timing and data recovery to provide 784 kbps, clear-channel, “data pipe” transmission. The Data Pump provides Near-End Cross-Talk (NEXT) performance in excess of that required over all ANSI and ETSI test loops. Typical transmission range on 26 AWG (0.4 mm) cable exceeds 13 kft (4 km) in a noise-free environment or 9.5 kft (2.9 km) with ANSI-specified noise levels. The Data Pump meets the requirements of Bellcore TA-NWT-001210, ANSI T1 Technical Report No. 28-1994 and ETSI ETR-152. It provides one end of a single-channel HDSL transmission system from the twisted pair interface back to the Data Pump/HDSL data interface. The Data Pump can be used at either the HTU-R or the HTU-C end of the interface. Applications s T1 (2-pair) and fractional T1 transport s N-channel digital pair-gain Product Features s Wireless base station to switch interface s Campus and private networking s Fully integrated, 2-chip set for interfacing to 2-wire HDSL lines at 784 kbps s Single +5 V power supply s Integrated line drivers, filters and hybrid circuits result in greatly reduced external logic and simplified support circuitry requirements s Simple line interface circuitry, via transformer coupling, to twisted pair line s Internal ACC voltage reference s Converts serial binary data to scrambled 2B1Q encoded data s Self-contained activation/start-up state machine for simplified single loop designs s Programmable for either central office (HTU-C) or remote site (HTU-R) applications s s Compliant with: s – Bellcore TA-NWT-001210 s – ANSI HDSL Technical Report No. 281994 s – ETSI ETR-152 (1995) s – ITU G.991.1 s Design allows for operation in either Software Control or stand-alone Hardware Control mode s Typical power consumption is less than 1.0 W allowing remote power feeding for repeater and HTU-R equipment s Input or Output Reference Clock of 12.544 MHz s Digital representation of receive signal level and noise margin values available for SNR controlled activation As of January 15, 2001, this document replaces the Level One document SK70704/SK70706 — 784 Kbps HDSL Data Pump Chip Set. Order Number: 249192-001 January 2001 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitnes.


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