CDP1883

CDP1883, CDP1883C March 1997 CMOS 7-Bit Latch and Decoder Memory Interfaces Description The CDP1883 is a CMOS 7-bit memory latch and decoder circuit intended for use in CDP1800-series microprocessor systems. It can serve as a direct interface between the multiplexed address bus of this system and up to four 8K x 8-bit memories to implement a 32K-byte memory system. With four 4K x 8-bit memories, a 16K-byte system can be decoded. The device is also compatible with non-multiplexed address bus microprocessors. By connecting the clock input to VDD, the latches are in the data-following mode and the decoded outputs can be used in general-purpose memory-system applications. The CDP1833 is compatible with CDP1800-series microprocessors operating at maximum clock frequency. The CDP1883 and CDP1883C are functionally identical. They differ in that the CDP1883 has a recommended operating voltage range of 4V to 10.5V and the C version has a recommended operating voltage range of 4V to 6.5V. The CDP1883 and CDP1883C are supplied in 20 lead dualin-line plastic packages (E Suffix). Features Performs Memory Address Latch and Decoder Functions Multiplexed or Non-Multiplexed Interfaces Directly with the CDP1800-Series Microprocessors Allows Decoding for Systems Up to 32K Bytes Ordering Information 5V 10V TEMP. RANGE -40oC to +85oC PACKAGE PDIP PKG. NO. E20.3 CDP1883CE CDP1883E Pinout CDP1883, CDP1883C (PDIP) TOP VIEW CLOCK MA0 MA1 MA2 MA3 MA4 MA5 MA6 CE 1 2 3 4 5 6 7 8 9 20 VDD 19...