CDP1826C

CDP1826C March 1997 CMOS 64-Word x 8-Bit Static RAM Description The CDP1826C is a general purpose, fully static, 64-word x 8-bit random-access memory, for use in CDP1800-series or other microprocessor systems where minimum component count and/or price performance and simplicity in use are desirable. The CDP1826C has 8 common data input and data-output terminals with three-state capability for direct connection to a standard bidirectional data bus. Two chip-select inputs - CS1 and CS2 - are provided to simplify memory-system expansion. An additional select pin, CS/A5, is provided to enable the CDP1826C to be selected directly from the CDP1800 multiplexed address bus without additional latching or decoding. In an 1800 system, the CS/A5 pin can be tied to any MA address line from the CDP1800 processor. A TPA input is provided to latch the high-order bit of this address line as a chip-select for the CDP1826C. If this CS/A5 input is latched high, and if CS = 1 and CS2 = 0 at the appropriate time in the memory cycle, the CDP1826C will be enabled for writing or reading. In a non-1800 system, the TPA pin can be tied high, and the CS/A5 pin can be used as a normal address input. The six input-address buffers are gated with the chip-select function to reduce standby current when the device is deselected, as well as to provide for a simplified power down mode by reducing address buffer sensitivity to long fall times from address drivers which are being powered down. Two memory control s...