K4S643232H-TC-L55

SDRAM 64Mb H-die (x32) CMOS SDRAM 64Mb H-die (x32) SDRAM Specification Revision 1.3 February 2004 *Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev. 1.3 February. 2004 SDRAM 64Mb H-die (x32) Revision History Revision 0.0 (June, 2003) - Target spec First release. Revision 0.1 (July, 2003) - Delete speed 4.5ns. Revision 0.2 (September, 2003) - Preliminary spec release. Revision 1.0 (November, 2003) - Final spec release Revision 1.1 (December, 2003) - Corrected typo Revision 1.2 (December, 2003) - Modified load cap 50pF -> 30pF & Typo Revision 1.3 (February, 2004) - Corrected typo. CMOS SDRAM - 2 - Rev. 1.3 February. 2004 SDRAM 64Mb H-die (x32) 512K x 32Bit x 4 Banks SDRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock. Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period(4K Cycle) CMOS SDRAM GENERAL DESCRIPTION The K4S643232H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on ever...