Document
NB3V63143G
1.8 V Programmable OmniClock Generator
with Single Ended (LVCMOS) and Differential (LVDS/HCSL) Outputs with Individual Output Enable and Individual VDDO
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The NB3V63143G, which is a member of the OmniClock family, is
a one−time programmable (OTP), low power PLL−based clock generator that supports any output frequency from 8 kHz to 200 MHz. The device accepts fundamental mode parallel resonant crystal or a single ended (LVCMOS) reference clock as input. It generates either
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QFN16 CASE 485AE
three single ended (LVCMOS) outputs, or one single ended output and one differential (LVDS/HCSL) output. The output signals can be
MARKING DIAGRAM
modulated using the spread spectrum feature of the PLL (programmable spread spectrum type, deviation and rate) for applications demanding low electromagnetic interference (EMI). Individual output enable pins OE[2:0] are available to enable/disable
3V631 43Gxx ALYWG
G
the outputs. Individual output voltage pins VDDO[2:0] are available
to independently set the output voltage of each output. Up to four different configurations can be written into the device memory. Two selection pins (SEL[1:0]) allow the user to select the configuration to use. Using the PLL bypass mode, it is possible to get a copy of the input clock on any or all of the outputs. The device can be powered
3V63143G xx
A L Y
= Specific Device Code = Specific Program Code (Default
‘00’ for Unprogrammed Part) = Assembly Location = Wafer Lot = Year
down using the Power Down pin (PD#). It is possible to program the
W
= Work Week
internal input crystal load capacitance and the output drive current
G
= Pb−Free Package
provided by the device. The device also has automatic gain control
(Note: Microdot may be in either location)
(crystal power limiting) circuitry which avoids the device overdriving the external crystal.
ORDERING INFORMATION
See detailed ordering and shipping information on page 20 of
this data sheet.
Features
• Member of the OmniClock Family of Programmable
• Programmable Internal Crystal Load Capacitors
Clock Generators
• Operating Power Supply: 1.8 V ± 0.1 V
• Programmable Output Drive Current for Single Ended
Outputs
• I/O Standards
• Power Saving Mode through Power Down Pin
♦ Inputs: LVCMOS, Fundamental Mode Crystal
• Programmable PLL Bypass Mode
♦ Outputs: 1.8 V LVCMOS ♦ Outputs: LVDS and HCSL
• 3 Programmable Single Ended (LVCMOS) Outputs
from 8 kHz to 200 MHz
• 1 Programmable Differential Clock Output up to
200 MHz
• Input Frequency Range
• Programmable Output Inversion • Programming and Evaluation Kit Available for Field
Programming and Quick Evaluation
• Temperature Range −40°C to 85°C • Packaged in 16−pin QFN • These are Pb−Free Devices
♦ Crystal: 3 MHz to 50 MHz ♦ Reference Clock: 3 MHz to 200 MHz
Typical Applications
• eBooks and Media Players
• Configurable Spread Spectrum Frequency Modulation
• Smart Wearables, Smart Phones, Portable Medical and
Parameters (Type, Deviation, Rate)
Industrial Equipment
• Individual Output Enable Pins
• Set Top Boxes, Printers, Digital Cameras and
• Independent Output Voltage Pins
Camcorders
© Semiconductor Components Industries, LLC, 2016
January, 2016 − Rev. 2
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Publication Order Number: NB3V63143G/D
NB3V63143G
BLOCK DIAGRAM
VDD PD# SEL0 SEL1
Reference XIN/ CLKIN Clock
Crystal
XOUT
Input Decoder
Crystal/Clock Control
Clock Buffer/ Crystal
Oscillator And AGC
PLL Block
Phase Detector
Configuration Memory
Frequency and SS
Output control
Output Divider
Charge Pump
Feedback Divider
VCO
Output Divider
PLL Bypass Mode
Output Divider
CMOS/ DIFF buffer
CMOS/ DIFF buffer
CMOS buffer
GND GNDO
Notes: 1. CLK0 and CLK1 can be configured to be one LVDS or HCSL output, or two single ended LVCMOS outputs. 2. Dotted lines are the programmable control signals to internal IC blocks. 3. OE[2:0], SEL[1:0] have internal pull up resistors. PD# has internal pull down resistor.
Figure 1. Simplified Block Diagram
PIN FUNCTION DESCRIPTION
VDDO0 CLK0 OE0 VDDO1 CLK1 OE1 VDDO2 CLK2 OE2
SEL0 SEL1 VDDO2 CLK2
XIN/CLKIN 1
16 15 14 13
NB3V63143G
12 VDD
XOUT 2 PD# 3
GNDO (EPAD)
11 VDDO1 10 CLK1
GND 4
9 CLK0
5 67 8
OE0 OE1 OE2 VDDO0
Figure 2. Pin Connections (Top View) − QFN16 (with EPAD)
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NB3V63143G
Table 1. PIN DESCRIPTION
Pin No.
Pin Name
Pin Type
1 XIN/CLKIN
Input
2 XOUT 3 PD#
Output Input
4 5, 6, 7
8 9
GND OE[2:0]
VDDO0 CLK0
Ground Input
Power SE/DIFF Output
10
CLK1
SE/DIFF Output
11 VDDO1 12 VDD 13 CLK2
14 15, 16
VDDO2 SEL[1:0]
Power Power SE Output
Power Input
EPAD
GNDO
Ground
Description
3 MHz to 50 MHz crystal input connection or an external single ended reference input clock between 3 MHz and 200 MHz.
Crystal output. Float this pin when external reference clock is connected at XIN.
Asynchronous LVCMOS input. Active Low Master Reset to disable the device and set outputs Low. Internal pull−down resistor. This pin needs to be pulled High for normal ope.