Document
SHARC+ Dual-Core DSP with Arm Cortex-A5
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
SYSTEM FEATURES
Dual enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 5 Mb (640 kB) Level 1 (L1) SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short-word, word, long-word addressed
Arm Cortex-A5 core 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle 32 kB L1 instruction cache/32 kB L1 data cache 256 kB Level 2 (L2) cache with parity
Powerful DMA system On-chip memory protection Integrated safety features
19 mm × 19 mm 349/529 BGA (0.8 pitch), RoHS compliant Low system power across automotive temperature range
MEMORY
Large on-chip L2 SRAM with ECC protection, up to 256 kB On-chip L2 ROM (512 kB) Two Level 3 (L3) interfaces optimized for low system power,
providing a 16-bit interface to DDR3 (supporting 1.5 V capable DDR3L devices), DDR2, or LPDDR1 SDRAM devices
ADDITIONAL FEATURES
Security and Protection Cryptographic hardware accelerators Fast secure boot with IP protection Support for Arm TrustZone
Accelerators High performance pipelined FFT/IFFT engine FIR, IIR, HAE, SINC offload engines
AEC-Q100 qualified for automotive applications
SYSTEM CONTROL
SECURITY AND PROTECTION SYSTEM PROTECTION (SPU)
SYSTEM MEMORY PROTECTION UNIT (SMPU)
FAULT MANAGEMENT Arm® TrustZone® SECURITY
DUAL CRC WATCHDOGS OTP MEMORY THERMAL MONITOR UNIT (TMU)
PROGRAM FLOW SYS EVENT CORE 0 (GIC) SYS EVENT CORES 1-2 (SEC) TRIGGER ROUTING (TRU)
CLOCK, RESET, AND POWER CLOCK GENERATION (CGU)
CLOCK DISTRIBUTION UNIT (CDU)
REAL TIME CLOCK (RTC) RESET CONTROL (RCU) POWER MANAGEMENT (DPM)
DEBUG UNIT Arm® CoreSightTM WATCHPOINTS (SWU)
CORE 0
Arm® Cortex®-A5
L1 CACHE 32 kB L1 I-CACHE 32 kB L1 D-CACHE
L2 CACHE 256 kB (PARITY)
CORE 1
S
L1 SRAM (PARITY) 5 Mb (640 kB) SRAM/CACHE
CORE 2
S
L1 SRAM (PARITY) 5 Mb (640 kB) SRAM/CACHE
SYSTEM CROSSBAR AND DMA SUBSYSTEM
L3 MEMORY INTERFACES
DDR3 DDR2 LPDDR1
DDR3 DDR2 LPDDR1
16 DATA
16 DATA
SYSTEM L2 MEMORY
SRAM (ECC) 2 Mb (256 kB)
ROM 2 Mb (256 kB)
ROM 2 Mb (256 kB)
SYSTEM ACCELERATION
DSP FUNCTIONS (FFT/IFFT, FIR, IIR, HAE/SINC)
ENCRYPTION/DECRYPTION
PERIPHERALS
SIGNAL ROUTING UNIT (SRU)
2×2 PRECISION CLOCK GENERATORS
ASRC FULL SPORT
2×4 PAIRS
2×4
2x DAI 2x PIN BUFFER
2×1 S/PDIF Rx/Tx
40–28
3× I2C 2× LINK PORTS 2× SPI + 1× QUAD SPI
3× UARTs 1× EPPI
3× ePWM
8× TIMERS + 1× COUNTER
G
ADC CONTROL MODULE
P
(ACM)
I
ASYNC MEMORY (16-BIT)
O
2× CAN2.0
SD/SDIO/eMMC
MLB 3-PIN 2× EMAC
SINC FILTER 8x SHARC FLAGS
2× USB 2.0 HS MLB 6-PIN
PCIe2.0 (1 lane)
HADC (8 CHAN, 12-BIT)
6
102–80
10 6 7 8
Figure 1. Processor Block Diagram
SHARC, SHARC+, and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
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ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
TABLE OF CONTENTS
System Features ....................................................... 1 Memory ................................................................ 1 Additional Features .................................................. 1 Table of Contents ..................................................... 2 Revision History ...................................................... 2 General Description ................................................. 3
Arm Cortex-A5 Processor ....................................... 5 SHARC Processor ................................................. 6 SHARC+ Core Architecture .................................... 8 System Infrastructure ........................................... 10 System Memory Map ........................................... 11 Security Features ................................................ 14 Security Features Disclaimer .................................. 15 Safety Features ................................................... 15 Processor Peripherals ........................................... 15 System Acceleration ............................................ 20 System Design .................................................... 21 System Debug .................................................... 23 Development Tools ............................................. 24 Additional Information ........................................ 25 Related Signal Chains ............