AD9993

Data Sheet Integrated Mixed-Signal Front End (MxFE) AD9993 FEATURES Quad 14-bit 250 MSPS ADC SFDR = 83 dBc at 87 MHz input Dual 14-bit 500 MSPS DAC SFDR = 75 dBc at 20 MHz output On-chip PLL clock synthesizer Low power 1536 mW, 1 GHz master clock, on-chip synthesizer 500 MHz double data rate (DDR) LVDS interfaces for DACs and ADCs Small 12 mm × 12 mm lead-free BGA package APPLICATIONS Point to point microwave backhaul radios Wireless repeaters GENERAL DESCRIPTION The AD9993 is a mixed-signal front-end (MxFE®) device that integrates four 14-bit ADCs and two 14-bit DACs. Figure 1 shows the block diagram of the MxFE. The MxFE is programmable using registers accessed via a serial peripheral interface (SPI). ADC and DAC datapaths include FIFO buffers to absorb phase differences between LVDS lane clocks and the data converter sampling clocks. The MxFE DACs are part of the Analog Devices, Inc., high speed CMOS DAC core family. These DACs are designed to be used in wide bandwidth communication system transmitter (Tx) signal chains. The MxFE ADCs are multistage pipelined CMOS ADC cores designed for use in communications receivers. FUNCTIONAL BLOCK DIAGRAM 2 14 ADC_A 2 14 ADC_B 14 4 DCO CLOCK STROBE LVDS BUFFER DOUT3A_x TO DOUT0A_x DOUT3B_x TO DOUT0B_x DOUT3C_x TO DOUT0C_x DOUT3D_x TO DOUT0D_x DCO_x STROBE_x 2 14 ADC_C DIGITAL –ADC AND DAC DATAPATHS 14 DIN6A_x TO DIN0A_x 2 ADC_D 14 –CONTROLS –SPI REGISTERS LVDS BUFFER DIN6B_x TO DIN0B_x –FIFO BUFFERS DCI CLOCK DC...