AD6672

Data Sheet FEATURES 11-bit, 250 MSPS output data rate Performance with NSR enabled SNR: 75.2 dBFS in a 55 MHz band to 185 MHz at 250 MSPS SNR: 72.8 dBFS in an 82 MHz band to 185 MHz at 250 MSPS Performance with NSR disabled SNR: 66.4 dBFS up to 185 MHz at 250 MSPS SFDR: 87 dBc up to 185 MHz at 250 MSPS Total power consumption: 358 mW at 250 MSPS 1.8 V supply voltages LVDS (ANSI-644 levels) outputs Integer 1-to-8 input clock divider (625 MHz maximum input) Internal ADC voltage reference Flexible analog input range 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) Serial port control Energy saving power-down modes APPLICATIONS Communications Diversity radio and smart antenna (MIMO) systems Multimode digital receivers (3G) WCDMA, LTE, CDMA2000 WiMAX, TD-SCDMA I/Q demodulation systems General-purpose software radios IF Receiver AD6672 GENERAL DESCRIPTION The AD6672 is an 11-bit intermediate receiver with sampling speeds of up to 250 MSPS. The AD6672 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired. The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent perform...