ST3407SRG

ST3407SRG P Channel Enhancement Mode MOSFET -3.6A DESCRIPTION ST3407SRG is the P-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook computer power management, other battery powered circuits, and low in-line power loss are required. The product is in a very small outline surface mount package. PIN CONFIGURATION SOT-23 3 D GS 12 FEATURE -30V/-4.0A, RDS(ON) = 54mΩ (Typ.) @VGS = -10V -30V/-3.2A, RDS(ON) = 72mΩ @VGS = -4.5V Super high density cell design for extremely low RDS(ON) Exceptional on-resistance and maximum DC current capability SOT-23 package design 1.Gate 2.Source 3.Drain PART MARKING SOT-23 3 A7YA 12 Y: Year Code A: Process Code STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA www.stansontech.com ST3407SRG 2006. V1 ST3407SRG P Channel Enhancement Mode MOSFET -3.6A ABSOULTE MAXIMUM RATINGS (Ta = 25℃ Unless otherwise noted ) Parameter Symbol Typical Drain-Source Voltage Gate-Source Voltage Continuous Drain CurrentTJ=150℃) TA=25℃ TA=70℃ Pulsed Drain Current VDSS VGSS ID IDM -30 ±20 -3.6 -3.0 -15 Continuous Source Current (Diode Conduction) Power Dissipation TA=25℃ TA=70℃ Operation Junction Temperature IS PD TJ -1.0 1.20 0.8 150 Storage Temperature Range TSTG -55/150 Ther...