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A3R1GE4EGF Dataheets PDF



Part Number A3R1GE4EGF
Manufacturers Zentel
Logo Zentel
Description 1Gb DDRII SDRAM
Datasheet A3R1GE4EGF DatasheetA3R1GE4EGF Datasheet (PDF)

A3R1GE4EGF 1Gb DDRII Synchronous DRAM 1Gb DDRII SDRAM Specification A3R1GE4EGF Zentel Electronics Corp. Revision 1.0 Apr., 2010 Specifications • Density: 1G bits • Organization ⎯ 8M words × 16 bits × 8 banks (A3R1GE4EGF) • Package ⎯ 84-ball FBGA(μBGA) (A3R1GE4EGF) ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 1.8V ± 0.1V • Data rate: 800Mbps/667Mbps (max.) ⎯ 800Μbps/667Mbps(max) • 2KB page size (A3R1GE4EGF) ⎯ Row address: A0 to A12 ⎯ Column address: A0 to A9 • Eight internal banks.

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A3R1GE4EGF 1Gb DDRII Synchronous DRAM 1Gb DDRII SDRAM Specification A3R1GE4EGF Zentel Electronics Corp. Revision 1.0 Apr., 2010 Specifications • Density: 1G bits • Organization ⎯ 8M words × 16 bits × 8 banks (A3R1GE4EGF) • Package ⎯ 84-ball FBGA(μBGA) (A3R1GE4EGF) ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 1.8V ± 0.1V • Data rate: 800Mbps/667Mbps (max.) ⎯ 800Μbps/667Mbps(max) • 2KB page size (A3R1GE4EGF) ⎯ Row address: A0 to A12 ⎯ Column address: A0 to A9 • Eight internal banks for concurrent operation • Interface: SSTL_18 • Burst lengths (BL): 4, 8 • Burst type (BT): ⎯ Sequential (4, 8) ⎯ Interleave (4, 8) • /CAS Latency (CL): 3, 4, 5, 6 • Precharge: auto precharge option for each burst access • Driver strength: normal/weak • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/64ms ⎯ Average refresh period 7.8μs at 0°C ≤ TC ≤ +85°C 3.9μs at +85°C < TC ≤ +95°C • Operating case temperature range ⎯ TC = 0°C to +95°C A3R1GE4EGF 1Gb DDRII Synchronous DRAM Features • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Posted /CAS by programmable additive latency for better command and data bus efficiency • Off-Chip-Driver Impedance Adjustment and On-Die- Termination for better signal quality • Programmable RDQS, /RDQS output for making × 8 organization compatible to × 4 organization • /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation Revision 1.0 Zentel Electronics Corporation reserve the right to change products or specification without notice. Page 1 / 76 Apr., 2010 Ordering Information Mask Part number version A3R1GE4EGF-G8E A3R1GE4EGF-G6E E Organization (words × bits) 64M × 16 A3R1GE4EGF 1Gb DDRII Synchronous DRAM Internal Banks 8 Speed bin (CL-tRCD-tRP) DDR2-800 (5-5-5) DDR2-667 (5-5-5) Package 84-ball FBGA Part Number Type Designation Code A 3 R 1G E 4 E G F - G 6E Speed Environment Code 8E:DDR2-800(5-5-5) 6C:DDR2-667(4-4-4) 6E:DDR2-667(5-5-5) 5C:DDR2-533(4-4-4) 4A:DDR2-400(3-3-3) G:Lead free Blank: Regular Package Type F:FBGA Process Generation G:0.65um Die Rev Organization 2:X4; 3:X8; 4:X16 Product Group E:DDR2 Density 1G:1Gb Interface R:1.8V SSTL_18 Memory Type 3:DRAM Zentel Memory Revision 1.0 Page 2 / 76 Apr., 2010 Pin Configurations /xxx indicates active low signal. A3R1GE4EGF 1Gb DDRII Synchronous DRAM Pin name A0 to A12 BA0, BA1, BA2 DQ0 to DQ15 DQS,/DQS UDQS, /UDQS LDQS, /LDQS /CS /RAS,/CAS,/WE CKE CK,/CK DM UDM, LDM Function Address inputs Bank select Data input/output Differential data strobe Chip select Command input Clock enable Differential clock input Write data mask Notes: 1.Not internally connected with die. 2. Don’t use other than reserved functions. Pin name ODT VDD VSS VDDQ VREF VDDL VSSDL NC*1 NU*2 Function ODT control Supply voltage for internal circuit Ground for DQ circuit Supply voltage for DQ circuit Input reference voltage Supply voltage for DLL circuit Ground for DLL circuit No connection Not usable Revision 1.0 Page 3 / 76 Apr., 2010 CONTENTS A3R1GE4EGF 1Gb DDRII Synchronous DRAM Specifications ................................................................................................................................ 1 Features ........................................................................................................................................ 1 Ordering Information ..................................................................................................................... 2 Part Number.................................................................................................................................. 2 Pin Configurations......................................................................................................................... 3 Electrical Specifications................................................................................................................. 5 Block Diagram............................................................................................................................... 25 Pin Function .................................................................................................................................. 26 Command Operation..................................................................................................................... 28 Simplified State Diagram......................................................................................


PFR10100CTF A3R1GE4EGF SB22


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