SN54LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

SN54LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will pe.

Features

et) Load “1” (Set) Hold L H H H H J X h l h l LOGIC SYMBOL 14 1 3 J CP Q 12 7 5 J CP Q 9 H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Don’t Care l, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time l, h (q) = prior to the HIGH to LOW clock transition. K C Q D 2 13 10 K C Q D 6 8 VCC = PIN 4 GND = PIN 11 FAST AND LS TTL DATA 5-68 SN54/74LS73A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 M.