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 DataSheet (67.02KB)
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These N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devi.
48 A, 50 V. RDS(ON) = 0.022 Ω @ VGS= 10 V. Critical DC electrical parameters specified at elevated temperature. Rugged internal source-drain diode can eliminate the need for an external Zener diode transient suppressor. 175°C maximum junction temperature rating. High density cell design for extremely low RDS(ON). TO-220 and TO-263 (D2PAK) package for both through hole and surface mount applications. ______________________________________________________________________________ D G S Absolute Maximum Ratings Symbol VDSS VDGR VGSS ID Parameter Drain-Source Voltage T C = 25°C unless otherwi.
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Fairchild |
N-Channel Enhancement Mode Field Effect Transistor |
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Fairchild |
N-Channel Logic Level Enhancement Mode Field Effect Transistor |
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National |
N-Channel Enhancement Mode Power Fleid Effect Transistor |
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National |
N-Channel Enhancement Mode Power Fleid Effect Transistor |
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Fairchild |
N-Channel Logic Level Enhancement Mode Field Effect Transistor |
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ON Semiconductor |
P-Channel Logic Level Enhancement Mode Field Effect Transistor |
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Fairchild |
P-Channel Logic Level Enhancement Mode Field Effect Transistor |
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Fairchild |
N-Channel Enhancement Mode Field Effect Transistor |
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Fairchild |
N-Channel Logic Level Enhancement Mode Field Effect Transistor |
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Fairchild |
P-Channel Logic Level Enhancement Mode Field Effect Transistor |
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Fairchild |
N-Channel Logic Level Enhancement Mode Field Effect Transistor |
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Fairchild |
P-Channel Logic Level Enhancement Mode Field Effect Transistor |
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