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| Features |
• In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated inputs including four clock pins • Simple timing model — No fanout delays — No expander delays — No dedicated vs. I/O pin delays — No additional delay through PIM — No penalty for using full 16 product terms • • • • — No delay for steering or sharing product terms 3.3V and 5V versions PCI-compatible[1] Programmable bus-hold capabilities on all I/O. |
CY37064P84-200JC Cypress Semiconductor
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Cypress Semiconductor |
5V/ 3.3V/ ISR High-Performance CPLDs |
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Cypress Semiconductor |
5V/ 3.3V/ ISR High-Performance CPLDs |
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Cypress Semiconductor |
5V/ 3.3V/ ISR High-Performance CPLDs |
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Cypress Semiconductor |
5V/ 3.3V/ ISR High-Performance CPLDs |
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Cypress Semiconductor |
5V/ 3.3V/ ISR High-Performance CPLDs |
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Cypress Semiconductor |
5V/ 3.3V/ ISR High-Performance CPLDs |
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Cypress Semiconductor |
5V/ 3.3V/ ISR High-Performance CPLDs |
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Cypress Semiconductor |
5V/ 3.3V/ ISR High-Performance CPLDs |
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Cypress Semiconductor |
5V/ 3.3V/ ISR High-Performance CPLDs |
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Cypress Semiconductor |
5V/ 3.3V/ ISR High-Performance CPLDs |
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Cypress Semiconductor |
5V/ 3.3V/ ISR High-Performance CPLDs |
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Cypress Semiconductor |
5V/ 3.3V/ ISR High-Performance CPLDs |
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