uPD46185364B |
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Part Number | uPD46185364B |
Manufacturer | Renesas (https://www.renesas.com/) |
Description | R10DS0113EJ0200 Rev.2.00 Nov 09, 2012 The μPD46185084B is a 2,097,152-word by 8-bit, the μPD46185094B is a 2,097,152-word by 9-bit, the μPD46185184B is a 1,048,576-word by 18-bit and the μPD46185364... |
Features |
• 1.8 ± 0.1 V power supply • 165-pin PLASTIC BGA (13 x 15) • HSTL interface • PLL circuitry for wide output data valid window and future frequency scaling • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE operation • Four-tick burst for reduced address frequency • Two input clocks (K and K#) for precise DDR timing at clock rising edges only • Two output clocks (C and C#) for precise flight time and clock skew matching-clock and data delivered together to receiving device • Internally self-timed write control • Clock-stop cap... |
Document |
uPD46185364B Data Sheet
PDF 567.19KB |
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No. | Part # | Manufacture | Description | Datasheet |
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Renesas |
18M-BIT QDR II SRAM 2-WORD BURST OPERATION |
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Renesas |
18M-BIT QDR II SRAM 4-WORD BURST OPERATION |
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Renesas |
18M-BIT QDR II SRAM 2-WORD BURST OPERATION |
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Renesas |
18M-BIT QDR II SRAM 4-WORD BURST OPERATION |
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Renesas |
18M-BIT QDR II SRAM 2-WORD BURST OPERATION |
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Renesas |
18M-BIT QDR II SRAM 4-WORD BURST OPERATION |
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Renesas |
18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION |
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Renesas |
18M-BIT DDR II SRAM 2-WORD BURST OPERATION |
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Renesas |
18M-BIT DDR II SRAM 4-WORD BURST OPERATION |
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Renesas |
18M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION |
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