74LVC2G07 DUAL BUFFERS

74LVC2G07 DUAL BUFFERS

The 74LVC2G07 is a dual buffer gate with open drain outputs. The device is designed for operation with a power supply range of 1.65V to 5.5V. The input is tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is fully specified for partial power down application.

Features

 Wide Supply Voltage Range from 1.65V to 5.5V
 -24mA Output Drive at 3.0V
 CMOS Low Power Consumption
 IOFF Supports Partial-Power-Down Mode Operation
 Inputs Accept up to 5.5V
 ESD Protection Tested per JESD 22
 Exceeds 200-V Machine Model (A115)
 Exceeds 2000-V Human Body Model (A114)
 Exceeds 1000-V Charged Device Model (C101)
 Latch-Up Exceeds 100mA per JESD 78, Class I
 DFN1409 Package Designed as a Direct Replacement for Chip Scale Packaging
 Range of Package Options SOT26, SOT363, X1-DFN1010-6, X2-DFN1010-6, X2-DFN1409-6, and X2-DFN1410-6
 Leadless Packages Named per JESD30.