The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP2G06 is composed of two inverters with open drain outputs designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for pa.
Advanced Ultra Low Power (AUP) CMOS
Supply Voltage Range from 0.8V to 3.6V
- 4mA Output Drive at 3.0V
Low Static Power Consumption
IC < 0.9µA
Low Dynamic Power Consumption
CPD = 1.2pF Typical at 3.6V
Schmitt Trigger Action at All Inputs Make the Circuit Tolerant for
Slower Input Rise and Fall Time. The Hysteresis is Typically 250mV at VCC = 3.0V
IOFF Supports Partial-Power-Down Mode Operation
ESD Protection per JESD 22
Exceeds 200-V Machine Model (A115)
Exceeds 2000-V Human Body Model (A114)
Exceeds 1000-V Charged Device Model (C101)
Latch-Up Exceeds 100mA per JESD .
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No. | Part # | Manufacture | Description | Datasheet |
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NXP |
Low-power dual 2-input NAND gate |
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Diodes |
DUAL NAND GATE |
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nexperia |
Low-power dual 2-input NAND gate |
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nexperia |
Low-power dual 2-input NAND gate |
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Diodes |
DUAL NOR GATE |
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NXP |
Low-power Dual 2-input NOR Gate |
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nexperia |
Low-power dual 2-input NOR gate |
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NXP |
Low-power dual inverter |
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Diodes |
DUAL INVERTERS |
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nexperia |
Low-power dual inverter |
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nexperia |
Low-power dual inverter |
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nexperia |
Low-power dual inverter |
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nexperia |
Low-power inverting buffer |
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NXP Semiconductors |
Low-power dual buffer |
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Diodes |
DUAL BUFFERS |
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