H5TQ5163MFR-12 Datasheet

H5TQ5163MFR-12 512Mb DDR3 SDRAM

and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. 1 Revision History Revision No. History 0.1 Preliminary 0.2 Async/Sync Parameter addition 0.3 1) (sub)Part number change as Hynix New .

Features

and Ordering Information 1.1.1 Description 1.1.2 Features 1.1.3 Ordering Information 1.1.4 Ordering Frequency 1.2 Package Ballout 1.3 Row and Column Address Table : 512M/1G Fixed 1.4 Pin Functional Description 1.5 Programming the Mode Registers 1.6 DDR3 SDRAM Mode Register(MR0) 1.6.1 Burst Length, Type and Order 1.6.2 CAS Latency 1.6.3 Test Mode 1.6.4 DLL Reset 1.6.5 Write Recovery 1.6.6 Precharge PD DLL 1.7 DDR3 SDRAM Mode Register(MR1) 1.7.1 DLL Enable/Disable 1.7.2 Output Driver Impedance Control 1.7.3 ODT Rtt Values 1.7.4 Additive Latency(AL) 1.7.5 Write leveling 1.7.6 Output Disable 1.7.7.