STU435S P-Channel Logic Level Enhancement Mode Field Effect Transistor

STU435S P-Channel Logic Level Enhancement Mode Field Effect Transistor

Gr Pr STU/D435S Ver 1.0 S a mHop Microelectronics C orp. P-Channel Logic Level Enhancement Mode Field Effect Transistor PRODUCT SUMMARY V DSS -40V ID -38A R DS(ON) (m Ω) Max 17.5 @ VGS=10V 27 @ VGS=4.5V FEATURES Super high dense cell design for low R DS(ON). Rugged and reliable. Suface Mount P.

Features

Super high dense cell design for low R DS(ON). Rugged and reliable. Suface Mount Package. G S G D S STU SERIES TO - 252AA( D - PAK ) STD SERIES TO - 251 ( I - PAK ) ABSOLUTE MAXIMUM RATINGS ( T C=25 °C unless otherwise noted ) Symbol Parameter VDS VGS ID IDM EAS PD TJ, TSTG Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous -Pulsed Sigle Pulse Avalanche Energy Maximum Power Dissipation Operating Junction and Storage Temperature Range a Limit -40 ±20 Units V V A A A mJ W W °C TC=25°C TC=70°C c -38 -30.4 -115 156 TC=25°C TC=70°C 42 27 -55 to 150 THERMAL CHARACTERISTIC.