HY5RS123235FP-16 512M (16Mx32) GDDR3 SDRAM

HY5RS123235FP-16 512M (16Mx32) GDDR3 SDRAM

and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.3 / Feb. 2006 1 HY5RS123235FP Revision History Revision No. 0.1 0.2 History Defined target spec. Page 11) Add Cas Latency 11 Page 14).

Features

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• 2.2V +/-0.1V VDD/VDDQ power supply supports 900MHz 2.0V VDD/ VDDQ wide range min/max power supply supports 700/ 800MHz
• 1.8V VDD/ VDDQ wide range min/max power supply supports 500 / 600MHz
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• Single ended READ Strobe (RDQS) per byte Single ended WRITE Strobe (WDQS) per byte Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
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• Calibrated output driver Differential clock inputs (CK and CK#) Commands entered on each positive CK edge RDQS edge-aligned with data for READ; with WDQS center-aligned with data for WRITE
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• Eight.