H55S5122EFR-A3M 512Mbit (16Mx32bit) Mobile SDR Memory

H55S5122EFR-A3M 512Mbit (16Mx32bit) Mobile SDR Memory

and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.2 / Sep. 2010 1 il;o;nar 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122EFR Series / H55S5132EFR Series Document Title 4Bank x 4M x 32bits Synchrono.

Features

●
●
● Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK) MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - During burst Read or Write operation, a different bank is activated and burst Read or Write for that bank is performed - During auto precharge burst Read or Write, burst Read or Write for a different bank is performed Power Supply Voltage: VDD = 1.8V, VDDQ = 1.8V LVCMOS compatible I/O Interface Low Voltage interface .