H57V2582GTR-75J Datasheet

H57V2582GTR-75J 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O

and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Aug. 2009 1 111 Synchronous DRAM Memory 256Mbit H57V2582GTR-xxI Series Document Title 256Mbit (32M x8) Synchronous DRAM Revision History Revis.

Features

● Standard SDRAM Protocol Internal 4bank operation Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V All device pins are compatible with LVTTL interface Low Voltage interface to reduce I/O power 8,192 Refresh cycles / 64ms Programmable CAS latency of 2 or 3 Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst
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● -40oC ~ 85oC Operation Package Type : 54_Pin TSOPII This product is in compliance with the directive pertaining of RoHS.
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● ORDERING INFORMATION Part Number H57V2582GTR-60I H57V2582GTR-75I H5.