HEF4011B Quadruple 2-input NAND gate

HEF4011B Quadruple 2-input NAND gate

The HEF4011B provides the positive quadruple 2-input NAND function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. HEF4011B gates Fig.2 Pinning diagram. HEF4011BP(N): HEF4011BD(F): Fig.1 Functional diagram. HEF4011BT(D): 14-lead DIL; plas.

Features

Quadruple 2-input NAND gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays In → On Output transition times HIGH to LOW 5 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPHL; tPLH SYMBOL TYP 55 25 20 60 30 20 60 30 20 MAX 110 45 35 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns HEF4011B gates TYPICAL EXTRAPOLATION FORMULA 28 ns + (0,55 ns/pF) CL 14 ns + (0,23 ns/pF) CL 12 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL V.