The HEF4011B provides the positive quadruple 2-input NAND function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. HEF4011B gates Fig.2 Pinning diagram. HEF4011BP(N): HEF4011BD(F): Fig.1 Functional diagram. HEF4011BT(D): 14-lead DIL; plas.
Quadruple 2-input NAND gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays In → On Output transition times HIGH to LOW 5 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPHL; tPLH SYMBOL TYP 55 25 20 60 30 20 60 30 20 MAX 110 45 35 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns HEF4011B gates TYPICAL EXTRAPOLATION FORMULA 28 ns + (0,55 ns/pF) CL 14 ns + (0,23 ns/pF) CL 12 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL V.
Distributor | Stock | Price | Buy |
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No. | Part # | Manufacture | Description | Datasheet |
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1 | HEF4011B |
Philips |
Quadruple 2-input NAND gate | |
2 | HEF4011B |
nexperia |
Quad 2-input NAND gate | |
3 | HEF4011B-Q100 |
nexperia |
Quad 2-input NAND gate | |
4 | HEF4011UB |
NXP |
Quadruple 2-input NAND gate | |
5 | HEF40106B |
NXP |
Hex inverting Schmitt trigger | |
6 | HEF40106B |
Philips |
Hex inverting Schmitt trigger | |
7 | HEF40106B |
nexperia |
Hex inverting Schmitt trigger | |
8 | HEF40106B-Q100 |
nexperia |
Hex inverting Schmitt trigger | |
9 | HEF4012B |
NXP |
Dual 4-input NAND gate | |
10 | HEF4013B |
NXP |
Dual D-type flip-flop | |
11 | HEF4013B |
nexperia |
Dual D-type flip-flop | |
12 | HEF4013B-Q100 |
nexperia |
Dual D-type flip-flop | |
13 | HEF4014B |
NXP |
8-bit static shift register | |
14 | HEF4014B |
Philips |
8-bit static shift register | |
15 | HEF4014B |
nexperia |
8-bit static shift register |