H55S2562JFR-75M 256MBit MOBILE SDR SDRAM based on 4M x 4Bank x16 I/O

H55S2562JFR-75M 256MBit MOBILE SDR SDRAM based on 4M x 4Bank x16 I/O

and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.1 / July. 2009 1 11 www.DataSheet4U.com 256Mbit (16Mx16bit) Mobile SDR H55S2562JFR Series Document Title 4Bank x 4M x 16bits Synchronous DRAM Revi.

Features

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● Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK) MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - During burst Read or Write operation, a different bank is activated and burst Read or Write for that bank is performed - During auto precharge burst Read or Write, burst Read or Write for a different bank is performed
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● Power Supply Voltage: VDD = 1.8V, VDDQ = 1.8V LVCMOS compatible I/O Interface Low Vo.