H55S2532JFR-75M Datasheet

H55S2532JFR-75M 256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O

and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Nov. 2008 1 11256Mbit (8Mx32bit) Mobile SDR www.DataSheet4U.com H55S2622JFR Series H55S2532JFR Series Document Title 4Bank x 2M x 32bits Synchr.

Features

● Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK)
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● MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - During burst Read or Write operation, a different bank is activated and burst Read or Write for that bank is performed - During auto precharge burst Read or Write, burst Read or Write for a different bank is performed
● Power Supply Voltage: VDD = 1.8V, VDDQ = 1.8V LVCMOS compatible I/O Interface Low Voltage inte.