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 DataSheet (4.11MB)
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All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchrono.
The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
• Off-Chip-Driver impedance adjustment (OCD) and
• 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O On-Die-Termination (ODT) for better signal quality
• DRAM organizations with 4, 8 and 16 data in/outputs
• Auto-Precharge operation for read and write bursts
• Double Data Rate architecture: two data transfers per
• Auto-Refresh, Self-Refresh and power saving Powerclock cycle four internal banks for concurrent operation Down modes
• Programmable CAS Latency: 3, 4, 5 and 6
• Average Refresh Period 7.8 μs .
| Distributor | Stock | Price | Buy |
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| No. | Part # | Manufacture | Description | Datasheet |
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Qimonda |
256-Mbit Double-Data-Rate-Two SDRAM |
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Qimonda |
256-Mbit Double-Data-Rate-Two SDRAM |
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Qimonda |
256-Mbit Double-Data-Rate-Two SDRAM |
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Infineon Technologies AG |
256 Mbi t DDR2 SDRAM |
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Infineon Technologies AG |
256 Mbit DDR2 SDRAM |
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Infineon |
256-Mbit x16 GDDR2 DRAM |
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Infineon |
256-Mbit x16 GDDR2 DRAM |
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Infineon |
256-Mbit x16 GDDR2 DRAM |
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Infineon |
256-Mbit x16 GDDR2 DRAM |
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Infineon |
256-Mbit x16 GDDR2 DRAM |
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Infineon |
256-Mbit x16 GDDR2 DRAM |
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Infineon |
256-Mbit x16 GDDR2 DRAM |
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Qimonda AG |
256-Mbit x16 DDR2 SDRAM |
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Qimonda AG |
256-Mbit x16 DDR2 SDRAM |
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Qimonda AG |
256-Mbit x16 DDR2 SDRAM |
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