SIS5503 (SIS5501 - SIS5503) PCI System I/O

SIS5503 (SIS5501 - SIS5503) PCI System I/O

The SiS5501(PCMC) bridges between the host bus and the PCI local bus. The SiS5501 (PCMC) monitors each cycle initiated by the CPU, and forwards it to the PCI bus if the CPU cycle does not target the local memory. For the CPU or the PCI bus to the local memory cycles, the built-in Cache and DRAM Cont.

Features

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• Supports the 51060, 56766, 73590, 815100 MHz and 75 MHz Pentium Processor Supports M1 and Other Pentium Compatible CPU Supports the Pipelined Address Mode of the Pentium or the P54C Processor Integrated Second Level ( L2 ) Cache Controller - Write Through and Write Back Cache Modes - 8 bits or 7 bits Tag with Direct Mapped Organization - Supports Standard and Burst SRAMs - Supports 64 KBytes to 2 MBytes Cache Sizes - Cache Read/Write Cycle of 3-2-2-2 or 4-2-2-2 Using Standard SRAMs at 66 MHz - Cache Read/Write Cycle of 3-1-1-1 Using Burst SRAMs at 66 MHz
• Integrated DRAM Controller .