Pin name A0 to A13 A10 (AP) BA0, BA1, BA2 DQ0 to DQ63 /RAS /CAS /WE /CS0, /CS1 CKE0, CKE1 CK0, CK1 /CK0, /CK1 DQS0 to DQS7, /DQS0 to /DQS7 DM0 to DM7 SCL SDA SA0, SA1 VDD VDDSPD VREF VSS ODT0, ODT1 NC Function Address input Row address Column address Auto precharge Bank select address Data input/out.
• Double-data-rate architecture; two data transfers per clock cycle
• The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS .
Distributor | Stock | Price | Buy |
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No. | Part # | Manufacture | Description | Datasheet |
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1 | EBE21UE8ABFA |
Elpida Memory |
2GB Unbuffered DDR2 SDRAM DIMM | |
2 | EBE21UE8AADA |
Elpida Memory |
2GB DDR2 SDRAM SO-DIMM | |
3 | EBE21UE8ACFA |
Elpida Memory |
2GB Unbuffered DDR2 SDRAM DIMM | |
4 | EBE21UE8ACSA |
Elpida Memory |
2GB DDR2 SDRAM SO-DIMM | |
5 | EBE21UE8ACUA |
Elpida Memory |
2GB DDR2 SDRAM SO-DIMM | |
6 | EBE21UE8ACWA |
Elpida Memory |
2GB Unbuffered DDR2 SDRAM DIMM | |
7 | EBE21UE8ACWB |
Elpida Memory |
2GB Unbuffered DDR2 SDRAM DIMM | |
8 | EBE21UE8AEFA |
Elpida Memory |
2GB Unbuffered DDR2 SDRAM DIMM | |
9 | EBE21UE8AEFB |
Elpida Memory |
2GB Unbuffered DDR2 SDRAM DIMM | |
10 | EBE21UE8AESA |
Elpida Memory |
2GB DDR2 SDRAM SO-DIMM | |
11 | EBE21UE8AEWA |
Elpida Memory |
2GB Unbuffered DDR2 SDRAM DIMM | |
12 | EBE21UE8AFFA |
Elpida Memory |
2GB Unbuffered DDR2 SDRAM DIMM | |
13 | EBE21UE8AFSA |
Elpida Memory |
2GB DDR2 SDRAM SO-DIMM | |
14 | EBE21AD4AGFA |
Elpida Memory |
2GB Registered DDR2 SDRAM DIMM | |
15 | EBE21AD4AGFB |
Elpida Memory |
2GB Registered DDR2 SDRAM DIMM |