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EBE21UE8ABDA
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EBE21UE8ABDA 2GB DDR2 SDRAM SO-DIMM

Document Datasheet DataSheet (253.33KB)

EBE21UE8ABDA 2GB DDR2 SDRAM SO-DIMM

Pin name A0 to A13 A10 (AP) BA0, BA1, BA2 DQ0 to DQ63 /RAS /CAS /WE /CS0, /CS1 CKE0, CKE1 CK0, CK1 /CK0, /CK1 DQS0 to DQS7, /DQS0 to /DQS7 DM0 to DM7 SCL SDA SA0, SA1 VDD VDDSPD VREF VSS ODT0, ODT1 NC Function Address input Row address Column address Auto precharge Bank select address Data input/out.

Features


• Double-data-rate architecture; two data transfers per clock cycle
• The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS .

EBE21UE8ABDA EBE21UE8ABDA EBE21UE8ABDA
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