ASM5I2304B 3.3 V Zero Delay Buffer

ASM5I2304B 3.3 V Zero Delay Buffer

ASM5P2304B is a versatile, 3.3V zero-delay buffer designed to distribute workstation, datacom, telecom and other high-performance applications. It is available in an 8 pin package. The part Block Diagram FBK CLKA1 REF PLL CLKA2 /2 Extra Divider (-2) CLKB1 CLKB2 Alliance Semiconductor 2575 Aug.

Features

ƒ ƒ ƒ Zero input - output propagation delay, adjustable by capacitive load on FBK input. Multiple configurations - Refer “ASM5P2304B Configurations Table”. Input frequency range: 4MHz to 20MHz ƒ ƒ ƒ ƒ ƒ ƒ ƒ Output-output skew less than 200pS. Device-device skew less than 500pS. Two banks of four outputs. www.DataSheet4U.com ƒ Multiple low-skew outputs. ASM5P2304B has an on-chip PLL, which locks to an input clock, presented on the REF pin. The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to b.