561622ETP HY5DU561622ETP

561622ETP HY5DU561622ETP

and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 /June. 2006 1 www.DataSheet4U.com HY5DU56822E(L)TP HY5DU561622E(L)TP 1 Revision History Revision No. 1.0 1.1 First release Added.

Features

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• VDD, VDDQ = 2.5V +/- 0.2V for DDR200, 266, 333 VDD, VDDQ = 2.6V +0.1V / -0.2V for DDR400 All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ and DQS transition with CK transition DM mask write data-in at the both rising and fall.