CY7C1462AV33 (CY7C146xAV33) 36-Mbit Pipelined SRAM

CY7C1462AV33 (CY7C146xAV33) 36-Mbit Pipelined SRAM

The CY7C1460AV33/CY7C1462AV33 are 3.3 V, 1M × 36/2M × 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1460AV33/CY7C1462AV33 are equipped with the advance.

Features

■ Pin compatible and functionally equivalent to ZBT
■ Supports 250 MHz bus operations with zero wait states
❐ Available speed grades are 250, 200 and 167 MHz
■ Internally self timed output buffer control to eliminate the need to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte write capability
■ 3.3 V power supply
■ 3.3 V/2.5 V I/O power supply
■ Fast clock-to-output times
❐ 2.6 ns (for 250 MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self timed writes
■ CY7C1460AV33 available in JEDEC-standard Pb-free 100-pin TQFP and non Pb.