WED2ZL64512S Synchronous Pipeline NBL SRAM

WED2ZL64512S Synchronous Pipeline NBL SRAM

The WEDC SyncBurst - SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 32Mb Sync SRAM integrate two 512K x 32 SRAMs into a single BGA package to provide 512K x 64 configuration. All synchronous inputs pass through registers controlled by .

Features

 Fast clock speed: 166, 150, 133, and 100MHz
 Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
 Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
 Seperate +2.5V ± 5% power supplys for core I/O (VCC + VCCQ)
 Double Word Write Control
 Clock-controlled and registered addresses, data I/Os and control signals
 Packaging:
• 119 bump BGA package
 Low capacitive bus loading WED2ZL64512S DESCRIPTION The WEDC SyncBurst - SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 32Mb Sync SRAM integrate two 512K x 32 SRAMs into a sin.