EP314 (EP312 / EP314) Classic FPLDs

EP314 (EP312 / EP314) Classic FPLDs

The CMOS EPROM EP312 and EP324 devices have a versatile macrocell structure and I/O architecture, which allow them to implement highperformance logic functions effectively. The EP312 and EP324 input and macrocell features are a superset of features offered by PAL/GAL devices. Therefore, EP312 and E.

Features

s s s s s s s s s s s s s s High-performance EPLDs with 12 macrocells (EP312) or 24 macrocells (EP324)
  – Combinatorial speeds as fast as 25 ns
  – Counter frequencies of up to 33.3 MHz
  – Pipelined data rates of up to 66 MHz Multiple 20-pin PAL and GAL replacement and integration Device erasure and reprogramming with advanced, nonvolatile EPROM configuration elements Programmable registers providing D, T, JK, and SR flipflops with individual Clear and Clock controls Dual feedback on all macrocells for implementing buried registers with bidirectional I/O Programmable-AND/allocatable-OR structu.