74HC2G32; 74HCT2G32 The 74HC2G/HCT2G32 is a high-speed Si-gate CMOS device. The 74HC2G/HCT2G32 provides the dual 2-input OR function. TYPICAL SYMBOL tPHL/tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where: fi.
• Wide supply voltage range from 2.0 to 6.0 V
• Symmetrical output impedance
• High noise immunity
• Low power dissipation
• Balanced propagation delays
• Very small 8 pins package
• Output capability: standard
• ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 6.0 ns. DESCRIPTION
74HC2G32; 74HCT2G32
The 74HC2G/HCT2G32 is a high-speed Si-gate CMOS device. The 74HC2G/HCT2G32 provides the dual 2-input OR function.
TYPICAL SYMBOL tPHL/tPLH CI CPD Notes 1. CPD is used to determine the dynamic power d.
Distributor | Stock | Price | Buy |
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No. | Part # | Manufacture | Description | Datasheet |
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1 | 74HC2G32 |
nexperia |
Dual 2-input OR gate | |
2 | 74HC2G32-Q100 |
nexperia |
Dual 2-input OR gate | |
3 | 74HC2G32DC |
nexperia |
Dual 2-input OR gate | |
4 | 74HC2G32DP |
nexperia |
Dual 2-input OR gate | |
5 | 74HC2G34 |
NXP |
Dual Buffer Gate | |
6 | 74HC2G34 |
nexperia |
Dual buffer gate | |
7 | 74HC2G34-Q100 |
nexperia |
Dual buffer gate | |
8 | 74HC2G00 |
Philips |
Dual 2-input NAND gate | |
9 | 74HC2G00 |
nexperia |
Dual 2-input NAND gate | |
10 | 74HC2G00-Q100 |
nexperia |
Dual 2-input NAND gate | |
11 | 74HC2G00DC |
nexperia |
Dual 2-input NAND gate | |
12 | 74HC2G00DP |
nexperia |
Dual 2-input NAND gate | |
13 | 74HC2G02 |
NXP |
Dual 2-input NOR gate | |
14 | 74HC2G02 |
nexperia |
Dual 2-input NOR gate | |
15 | 74HC2G02-Q100 |
nexperia |
Dual 2-input NOR gate |