SN74LS273 Octal D Flip-Flop

SN74LS273 Octal D Flip-Flop

The SN74LS273 is an 8-Bit Parallel Register with a common Clock and common Master Reset. When the MR input is LOW, the Q outputs are LOW, independent of the other inputs. Information meeting the setup and hold time requirements of the D inputs is transferred to the Q outputs on the LOW-to-HIGH tran.

Features

ORDERING INFORMATION Device Package Shipping SN74LS273N PDIP−20 1440 Units/Box SN74LS273DW SOIC−WIDE 38 Units/Rail SN74LS273DWR2 SOIC−WIDE 2500/Tape & Reel SN74LS273M SOEIAJ−20 See Note 1 SN74LS273MEL SOEIAJ−20 See Note 1 1. For ordering information on the EIAJ version of the SOIC package, please contact your local ON Semiconductor representative. 1 Publication Order Number: SN74LS273/D SN74LS273 CONNECTION DIAGRAM DIP (TOP VIEW) VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND PIN NAMES CP D0 − D7 MR Q0 − Q7 Cl.