NBSG16MMNR2 2.5V/3.3VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer

NBSG16MMNR2 2.5V/3.3VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer

I/O − LVDS, CML, ECL, LVTTL, LVCMOS Input LVDS, CML, ECL, LVTTL, LVCMOS Input − − − − − − CML Output CML Output − − − − − − ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Description Internal 50 W Termination Pin. See Table 2. (Note 3) Inverted Differential Input (Note 3) Noninverted Differential.

Features

be left open. http://onsemi.com MARKING DIAGRAM* QFN−16 MN SUFFIX CASE 485G A L Y W SG 16M ALYW = Assembly Location = Wafer Lot = Year = Work Week *For additional marking information, refer to Application Note AND8002/D.
• Maximum Input Clock Frequency > 10 GHz Typical
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• Maximum Input Data Rate > 10 Gb/s Typical 120 ps Typical Propagation Delay 35 ps Typical Rise and Fall Times Positive CML Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V Negative CML Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V CML Output Le.