PHT6N06LT TrenchMOS transistor Logic level FET

PHT6N06LT TrenchMOS transistor Logic level FET

N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mounting. The device features very low on-state resistance and has integral zener diodes giving ESD protection. It is intended for use in DC-DC converters and general purpose switching app.

Features

very low on-state resistance and has integral zener diodes giving ESD protection. It is intended for use in DC-DC converters and general purpose switching applications. PHT6N06LT QUICK REFERENCE DATA SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Tsp = 25 ˚C Drain current (DC) Tamb = 25 ˚C Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V MAX. 55 5.5 2.5 8.3 150 150 UNIT V A A W ˚C mΩ PINNING - SOT223 PIN 1 2 3 4 gate drain source drain (tab) DESCRIPTION PIN CONFIGURATION 4 SYMBOL d g s 1 2 3 LIMITING VALUES Limit.