PEF20570 DSP Embedded Line and Port Interface Controller

PEF20570 DSP Embedded Line and Port Interface Controller

in the “DELIC-LC PEB 20570/DELIC-PB PEB 20571 Data Sheet, Version 3.1” but extends the operating conditions to the extended temperature range of -40°C to +85°C. The ordering code is: Table 2 Device Name DELIC-LC DELIC-PB DELIC-LC/DELIC-PB PEF Version Ordering Code Version Version 3.1 Version 3.1 Typ.

Features

C Clock System Synchronization” 1.1 Clocking the VIP in LT-T Mode by DELIC Layer 1 Clock 1 6 .3 8 4 M H z DCXO 8 kH z PD MUX R EFCLK D ivid e r XCLK 1 6 .3 8 4 M H z PLL D ivid e r D ivid e r 1 5 .3 6 M H z IN C L K OSC /1 0 C e n tra l O ffice R xP L L M ux VIP DELIC L1_CLK 1 .5 3 6 M H z REFCLK DELIC _refclk1 Figure 1 Clocking the VIP by using DELIC Layer 1 Clock When the Central Office is activated, its clock signal is retrieved by the RxPLL of the VIP and a 1.536 MHz reference signal is generated and used as input signal for the DELIC DCXO (pin XCLK). This signal is divided down.