IDT79R3051E RISControllers

IDT79R3051E RISControllers

Languages Clk2xIn Clock Generator Unit Master Pipeline Control System Control Coprocessor Exception/Control Registers Memory Management Registers BrCond(3:0) Integer CPU Core General Registers (32 x 32) ALU Shifter Int(5:0) Translation Lookaside Buffer (64 entries) Mult/Div Unit Address Adde.

Features

• Instruction set compatible with IDT79R3000A and IDT79R3001 MIPS RISC CPUs
• High level of integration minimizes system cost, power consumption — IDT79R3000A /IDT79R3001 RISC Integer CPU — R3051 features 4KB of Instruction Cache — R3052 features 8KB of Instruction Cache — All devices feature 2kB of Data Cache — “E” Versions (Extended Architecture) feature full function Memory Management Unit, including 64entry Translation Lookaside Buffer (TLB) — 4-deep write buffer eliminates memory write stalls — 4-deep read buffer supports burst refill from slow memory devices
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• — On-chip DMA a.