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4-BIT D LATCH The TTL/MSI SN54 / 74LS75 and SN54 / 74LS77 are latches used as temporary storage for binary information between processing units and input /output or indicator units. Information present at a data (D) input is transferred to the Q output when the Enable is HIGH and the Q output will f.
complementary Q and Q output from a 4-bit latch and is available in the 16-pin packages. For higher component density applications the SN54 / 74LS77 4-bit latch is available in the 14-pin package with Q outputs omitted. CONNECTION DIAGRAMS DIP (TOP VIEW)
Q0 16 Q1 15 Q1 14 E0
–1 GND 13 12 Q2 11 Q2 10 Q3 9
16
SN54/74LS75 SN54/74LS77
4-BIT D LATCH
LOW POWER SCHOTTKY
J SUFFIX CERAMIC CASE 620-09
1
SN54 / 74LS75 N SUFFIX PLASTIC CASE 648-08
1
1 Q0 Q0 14
2 D0 Q1 13
3 D1
4
5
E2
–3 VCC NC 10
6 D2 Q2 9
7 D3 Q3 8
8 Q3
16
E0
–1 GND 12 11
16 1
D SUFFIX SOIC CASE 751B-03
SN54 / 74LS77 J SUFF.
| Distributor | Stock | Price | Buy |
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Motorola Inc |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
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Texas Instruments |
DUAL J-K FLIP-FLOPS |
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Motorola |
10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS |
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Motorola Inc |
DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP |
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Texas Instruments |
Dual D-Type Positive-Edge Triggered Flip-Flops |
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Motorola Inc |
4-BIT D LATCH |
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Texas Instruments |
4-BIT BISTABLE LATCHE |
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Motorola Inc |
DUAL JK FLIP-FLOP WITH SET AND CLEAR |
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Texas Instruments |
DUAL J-K FLIP-FLOPS |
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Texas Instruments |
4-BIT BISTABLE LATCHE |
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Motorola Inc |
TRI-STATE OCTAL BUFFERS |
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Motorola Inc |
TRI-STATE OCTAL BUFFERS |
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Motorola Inc |
TRI-STATE OCTAL BUFFERS |
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Motorola Inc |
TRI-STATE OCTAL BUFFERS |
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Texas Instruments |
Quadruple 2-Input Positive-NAND Gates |
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