SN54LS259 8-BIT ADDRESSABLE LATCH

SN54LS259 8-BIT ADDRESSABLE LATCH

The SN54 / 74LS259 has four modes of operation as shown in the mode selection table. In the addressable latch mode, data on the Data line (D) is written into the addressed latch.The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. In the m.

Features

.L. 0.5 U.L. 0.25 U.L. 5 (2.5) U.L. A0, A1, A2 D E C Q0 to Q7 Address lnputs Data Input Enable (Active LOW) Input Clear (Active LOW) input Parallel Latch Outputs (Note b) 0.5 U.L. 0.5 U.L. 1.0 U.L. 0.5 U.L. 10 U.L. ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Curr.