P83CL882 80C51 Ultra Low Power ULP telephony controller

P83CL882 80C51 Ultra Low Power ULP telephony controller

ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pin configuration Pin description FUNCTIONAL DESCRIPTION Oscillator circuitry The CPU Interrupt controller Port control logic Timer 0 and Timer 1 event counters Timer 2 Watchdog Timer I2C-bus serial I/O (master/slave interface) MSK modem Interna.

Features

GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pin configuration Pin description FUNCTIONAL DESCRIPTION Oscillator circuitry The CPU Interrupt controller Port control logic Timer 0 and Timer 1 event counters Timer 2 Watchdog Timer I2C-bus serial I/O (master/slave interface) MSK modem Internal Data Memory Special Function Registers overview INSTRUCTION SET Instruction map APPLICATION INFORMATION Introduction Differences between P83CL882 and the Metalink EH emulation system The asynchronous handshake CPU 9 9.1 9.2 9.3 10 11 12 13 13.1 13.2 13.3 13.4 13.5 14 15 16 17 .